VINN_IN_BM=VINN_IN_BM_50PCNT, ADC_BM=ADC_BM_50PCNT, VREF_BM=VREF_BM_50PCNT, VINN_OUT_BM=VINN_OUT_BM_50PCNT, ADC_ORDER=ADC_ORDER_3ORDER
ADC core and reference setting regsiter
| ADC_BM | ADC bias current selection. 0 (ADC_BM_50PCNT): 50% 1 (ADC_BM_75PCNT): 75% 2 (ADC_BM_100PCNT): 100% 3 (ADC_BM_150PCNT): 150% 4 (ADC_BM_200PCNT): 200% 5 (ADC_BM_300PCNT): 300% |
| ADC_ORDER | 1 to enable SD ADC 2 order mode selection 0 (ADC_ORDER_3ORDER): 3 order 1 (ADC_ORDER_2ORDER): 2 order |
| DITHER_EN | 1 to enable SD ADC PN Sequence in chopper mode |
| CHOP_EN | 1 to enable SD ADC chopper |
| INV_CLK | 1 to invert SD ADC Output Clock |
| VREF_BM | SD ADC Reference Driver bias current selection. 0 (VREF_BM_50PCNT): 50% 1 (VREF_BM_75PCNT): 75% 2 (VREF_BM_100PCNT): 100% 3 (VREF_BM_150PCNT): 150% 4 (VREF_BM_200PCNT): 200% 5 (VREF_BM_300PCNT): 300% |
| VREF_BM_X3 | SD ADC Reference Driver bias current triple. |
| VINN_IN_BM | PGA VlNN Input Driver bias current selection. 0 (VINN_IN_BM_50PCNT): 50% 1 (VINN_IN_BM_75PCNT): 75% 2 (VINN_IN_BM_100PCNT): 100% 3 (VINN_IN_BM_150PCNT): 150% 4 (VINN_IN_BM_200PCNT): 200% 5 (VINN_IN_BM_300PCNT): 300% |
| VINN_OUT_BM | PGA VlNN Output Driver bias current selection. 0 (VINN_OUT_BM_50PCNT): 50% 1 (VINN_OUT_BM_75PCNT): 75% 2 (VINN_OUT_BM_100PCNT): 100% 3 (VINN_OUT_BM_150PCNT): 150% 4 (VINN_OUT_BM_200PCNT): 200% 5 (VINN_OUT_BM_300PCNT): 300% |
| VINN_OUT_BM_X3 | PGA VlNN Output Driver bias current triple. |
| ADC_BM_DIV2 | SD ADC bias current half. |